Skip to main content

6.5 组 5：跨 lane（unit: xlane，37 条）

shfl 与 quad（16 条）​

SHFL​

语法（Syntax）

shfl.idx                 rd:v rs1:v rs2:v
shfl.up                  rd:v rs1:v rs2:v
shfl.down                rd:v rs1:v rs2:v
shfl.xor                 rd:v rs1:v rs2:v
shfl.rot                 rd:v rs1:v rs2:v
shfl.up.vi               rd:v rs1:v imm:s8
shfl.down.vi             rd:v rs1:v imm:s8
shfl.xor.vi              rd:v rs1:v imm:s8
shfl.rot.vi              rd:v rs1:v imm:s8
shfl.bcast.vi            rd:v rs1:v imm:s8
shfl.bcast.vu            rd:v rs1:v rs2:u
shfl.up.vu               rd:v rs1:v rs2:u
shfl.down.vu             rd:v rs1:v rs2:u
shfl.xor.vu              rd:v rs1:v rs2:u
shfl.rot.vu              rd:v rs1:v rs2:u
变体编码延迟语义标志
shfl.idxR op opcode=0x2e f4=0x0fixed:6d = s1[s2 & 31]（源 lane 即使不活跃也读取）xl
shfl.upR op opcode=0x2e f4=0x1fixed:6j = lane - s2；d = (s2 <= lane) ? s1[j] : s1[lane]（delta 不截断）xl
shfl.downR op opcode=0x2e f4=0x2fixed:6j = lane + s2；d = (j < 32) ? s1[j] : s1[lane]（delta 不截断）xl
shfl.xorR op opcode=0x2e f4=0x3fixed:6d = s1[lane ^ (s2 & 31)]xl
shfl.rotR op opcode=0x2e f4=0x4fixed:6d = s1[(lane + s2) & 31]（cluster 32）xl
shfl.up.viI8 op opcode=0x30 f3=0x0fixed:6同 shfl.up，delta = imm[4:0]xl
shfl.down.viI8 op opcode=0x30 f3=0x1fixed:6同 shfl.down，delta = imm[4:0]xl
shfl.xor.viI8 op opcode=0x30 f3=0x2fixed:6d = s1[lane ^ imm[4:0]]xl
shfl.rot.viI8 op opcode=0x30 f3=0x3fixed:6d = s1[(lane + imm) & 31]xl
shfl.bcast.viI8 op opcode=0x30 f3=0x4fixed:6d = s1[imm[4:0]]xl
shfl.bcast.vuRU op opcode=0x32 f5=0x0fixed:6d = s1[u2 & 31]xl
shfl.up.vuRU op opcode=0x32 f5=0x1fixed:6同 shfl.up，delta = u2（不截断）xl
shfl.down.vuRU op opcode=0x32 f5=0x2fixed:6同 shfl.down，delta = u2（不截断）xl
shfl.xor.vuRU op opcode=0x32 f5=0x3fixed:6d = s1[lane ^ (u2 & 31)]xl
shfl.rot.vuRU op opcode=0x32 f5=0x4fixed:6d = s1[(lane + u2) & 31]xl
QUAD​

语法（Syntax）

quad.swizzle             rd:v rs1:v imm:u8

描述：d = s1[(lane & ~3) | imm 每 lane 2 位选择子]（quad 内广播 / 交换）

变体编码延迟标志
quad.swizzleI8 op opcode=0x30 f3=0x5fixed:6xl wqm

写 / 读 lane（4 条）​

WRITELANE​

语法（Syntax）

writelane                rd:v* rs2:u rs1:ln7

描述：d[lane7] = u2，其余 lane 不变（无视 EXEC；lane7 ≥ 32 → IllegalInsn 陷阱）

变体编码延迟标志
writelaneRU op opcode=0x32 f5=0x5fixed:6ei xl
READFIRST​

语法（Syntax）

readfirst                rd:u rs1:v

描述：U[d] = s1[最低活跃 lane]（EXEC = 0 → lane 0）

变体编码延迟标志
readfirstC op opcode=0x36 f5=0x4fixed:6xl re ur
READLANE​

语法（Syntax）

readlane                 rd:u rs1:v imm:u8
readlane.u               rd:u rs1:v rs2:u
变体编码延迟语义标志
readlaneCI op opcode=0x38 f4=0x0fixed:6U[d] = s1[imm & 31]（无视 EXEC）xl ei ur
readlane.uCU op opcode=0x3a f6=0x0fixed:6U[d] = s1[u2 & 31]（无视 EXEC）xl ei ur

导数（4 条）​

FDDX​

语法（Syntax）

fddx.fine.f32            rd:v rs1:v
fddx.coarse.f32          rd:v rs1:v
变体编码延迟语义标志
fddx.fine.f32R1 op opcode=0x34 f11=0x0fixed:6d = s1[lane|1] - s1[lane&~1]（quad 内 x 方向，fine）xl wqm fm
fddx.coarse.f32R1 op opcode=0x34 f11=0x2fixed:6d = s1[q+1] - s1[q+0]，q = lane & ~3（整个 quad 一值）xl wqm fm
FDDY​

语法（Syntax）

fddy.fine.f32            rd:v rs1:v
fddy.coarse.f32          rd:v rs1:v
变体编码延迟语义标志
fddy.fine.f32R1 op opcode=0x34 f11=0x1fixed:6d = s1[lane|2] - s1[lane&~2]（quad 内 y 方向，fine）xl wqm fm
fddy.coarse.f32R1 op opcode=0x34 f11=0x3fixed:6d = s1[q+2] - s1[q+0]，q = lane & ~3（整个 quad 一值）xl wqm fm

归约 / 扫描 / 投票（13 条）​

XSCAN​

语法（Syntax）

xscan.add.u32            rd:v rs1:v

描述：d = 活跃且 j <= lane 的 s1[j] 之和（包含前缀和；非活跃 lane 不写）

变体编码延迟标志
xscan.add.u32R1 op opcode=0x34 f11=0x4fixed:6xl re
BALLOT​

语法（Syntax）

ballot                   rd:u rs1:v

描述：U[d] = EXEC 内 s1 != 0 的 lane 掩码

变体编码延迟标志
ballotC op opcode=0x36 f5=0x0fixed:6xl re ur
VOTE​

语法（Syntax）

vote.any                 rd:u rs1:v
vote.all                 rd:u rs1:v
vote.eq                  rd:u rs1:v
变体编码延迟语义标志
vote.anyC op opcode=0x36 f5=0x1fixed:6U[d] = 任一活跃 lane s1 != 0 ? 1 : 0（EXEC = 0 → 0）xl re ur
vote.allC op opcode=0x36 f5=0x2fixed:6U[d] = 所有活跃 lane s1 != 0 ? 1 : 0（EXEC = 0 → 1）xl re ur
vote.eqC op opcode=0x36 f5=0x3fixed:6U[d] = 所有活跃 lane 的 s1 相等 ? 1 : 0（EXEC = 0 → 1）xl re ur
XRED​

语法（Syntax）

xred.add.u32             rd:u rs1:v
xred.min.i32             rd:u rs1:v
xred.max.i32             rd:u rs1:v
xred.min.u32             rd:u rs1:v
xred.max.u32             rd:u rs1:v
xred.and.b32             rd:u rs1:v
xred.or.b32              rd:u rs1:v
xred.xor.b32             rd:u rs1:v
变体编码延迟语义标志
xred.add.u32C op opcode=0x36 f5=0x5fixed:6U[d] = 活跃 lane 的 s1 之和（空集 → 0）xl re ur
xred.min.i32C op opcode=0x36 f5=0x6fixed:6U[d] = 活跃 lane 的有符号 min（空集 → INT_MAX）xl re ur
xred.max.i32C op opcode=0x36 f5=0x7fixed:6U[d] = 活跃 lane 的有符号 max（空集 → INT_MIN）xl re ur
xred.min.u32C op opcode=0x36 f5=0x8fixed:6U[d] = 活跃 lane 的无符号 min（空集 → 0xffffffff）xl re ur
xred.max.u32C op opcode=0x36 f5=0x9fixed:6U[d] = 活跃 lane 的无符号 max（空集 → 0）xl re ur
xred.and.b32C op opcode=0x36 f5=0xafixed:6U[d] = 活跃 lane 的 AND（空集 → 全 1）xl re ur
xred.or.b32C op opcode=0x36 f5=0xbfixed:6U[d] = 活跃 lane 的 OR（空集 → 0）xl re ur
xred.xor.b32C op opcode=0x36 f5=0xcfixed:6U[d] = 活跃 lane 的 XOR（空集 → 0）xl re ur